Functionals of Brownian bridges arising in the current mismatch in D/A-converters

Digital-to-analog converters (DAC) transform signals from the abstract digital domain to the real analog world. In many applications, DAC's play a crucial role. Due to variability in the production, various errors arise that influence the performance of the DAC. We focus on the current errors, which describe the fluctuations in the currents of the various unit current elements in the DAC. A key performance measure of the DAC is the Integrated Non-linearity (INL), which we study in this paper. There are several DAC architectures. The most widely used architectures are the thermometer, the binary and the segmented architectures. We study the two extreme architectures, namely, the thermometer and the binary architectures. We assume that the current errors are i.i.d. normally distributed, and reformulate the INL as a functional of a Brownian bridge. We then proceed by investigating these functionals. For the thermometer case, the functional is the maximal absolute value of the Brownian bridge, which has been investigated in the literature. For the binary case, we investigate properties of the functional, such as its mean, variance and density.Comment: 22 pages, 4 figures. Version 2 with Section 3.6 added, and Section 4 revised. To appear in "Probability in the Engineering and Informational Sciences

Flexible and self-calibrating current-steering digital-to-analog converters : analysis, classification and design

This research work proposes new concepts of flexibility and self-correction for currentsteering digital-to-analog converters (DACs) which allow the attainment of broad functional and performance specifications, high linearity, and reduced dependence on the fabrication processes. This work analytically investigates the DAC linearity with respect to the accuracy of the DAC unit elements. The main novelty of the proposed approach is in the application of the Brownian Bridge (BB) process to precisely describe the DAC Integrated-Non-Linearity (INL). The achieved results fill a gap in the general understanding of the most quoted DAC specification - the INL. Further, this work introduces a classification of the highly diverse current-steering DAC correction methods. The classification automatically points to methods that do not exist yet in the open literature (gaps). Based on the clues of the common properties and identified common techniques in the introduced classification, this work then proposes exemplary solutions to fill in the identified gaps. Further, this work systematically analyses self-calibration correction methods for the DAC mismatch errors. Their components are analyzed as three building blocks: selfmeasurement, error processing algorithm and self-correction block. This work systemizes their alternative implementations and the associated trade-offs. The findings are compared to the available solutions in the literature. The efficient calibration of the DAC binary currents is identified as an important missing method. This work proposes a new methodology for correcting the mismatch errors of both the nominally identical unary and the scaled binary DAC currents. Further, this work proposes a new concept for DAC flexibility. This concept is realized in a new flexible DAC architecture. The architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, flexible functionality and flexible performance. The parallel sub-DAC units form a mixed-signal platform that is capable of many DAC correction methods, including calibration, error mapping, data reshuffling, and harmonic distortion cancellation. This work presents the implementation and measurement results of three DAC testchip implementations in 250nm, 180nm, and 40nm standard CMOS IC technologies. The test-chips are used as a tool to practically investigate, validate, and demonstrate two main concepts of this thesis: self-calibration and flexibility. Particularly, the 180nm test-chip is the first reported DAC implementation that calibrates the errors of all its current sources and features flexibility, as suggested in this work. The calibration of all current sources makes the DAC accuracy independent of the tolerances of the manufacturing process. The overall DAC accuracy depends on a single design parameter – the correction step. The third test-chip is the first reported DAC implementation in 40nm CMOS process. A 12-bit DAC core in this test-chip occupies only 0.05mm2 of silicon area, which is the smallest reported area for a 12-bit current-steering DAC core

A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < —60dB up to 350MHz

This paper presents a very small area 12b IGSps self-calibrated current-steering DAC cell occupying just 0.037mm 2 in 40nm, while delivering SFDR>60dB up to 200MHz and IM3<-60dB up to 350MHz. The DAC architecture, selfcalibration apparatus and layout are specifically designed as a balance between small area, robustness, and high performance, so that embedding in VLSI is feasible. The small size of the DAC unit allows massive integration, which is demonstrated in this work by an array of 16 12b DAC units

Methods and systems for high frequency clock distribution

In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency sub-clocks for a destination in the VLSI system, distributing each lower-frequency sub-clock of the one or more pairs of lower-frequency sub-clocks to a corresponding channel coupled to the destination, and reconstructing a reference master clock signal at the destination from the one or more pairs of lower-frequency sub-clocks, wherein the reconstructed reference master clock signal replicates the original master clock signal

Two Self-Calibrating DAC Designs

This chapter presents the implementation and measurement results of two DAC test-chip implementations in 250 nm and 180 nm standard CMOS processes. The chapter considers the test-chips primarily from the calibration point of view. The measurement results show that the practical limit of the presented calibration easily exceeds the 14 bit level. The 250 nm and 180 nm test chips feature fully-integrated calibration engines. The first test-chip is a 12 bit 250 nm current-steering DAC with unary currents calibration. The second test-chip is a flexible 12 bit quad-core 180 nm current-steering DAC with both binary and unary currents calibration. This is the first reported DAC implementation that calibrates the errors of all its current sources

A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters

This paper investigates the beam squint of direct conversion phased array transmitters with quadrature modulation and digital beam-forming. Beam squint occurs due to frequency dependent beam forming and leads to signal deterioration. It is analyzed in terms of EVM and maximum bit-rate, using both analytical and numerical computation. Various results illustrate the dependencies of the error mechanism on key design parameters in mm-wave transmitters. It is shown that having 14 elements and 120° scanning angle limits the theoretical maximum bitrate by 84% We show that using partial symbol delay in baseband, the EVM can be improved up to-30dB for 10 elements and more, without any apparent disadvantages. Moreover the bitrate theoretical maximum is increased by 4 times